1. Field of the Invention
The present invention relates to a digital transmission apparatus, especially one which uses a forward error correction (FEC) method together with a differential coding and modulation method to which a differential detection, which is effective for circuit miniaturization and reduction of power consumption, can be applied.
2. Description of the Related Art
In the case of using an FEC method together with the differential coding and modulation method for performing the digital transmission, i) at the transmission side, after FEC encoding is performed, differential encoding and phase modulation are performed; and ii) at the receiving side, after differential detection, or a set of coherent detection and differential decoding are performed, FEC decoding is performed. Such digital transmission apparatuses are generally called "digital transceivers" in the radio transmission field.
In digital signal transmission using such a method, the major problem is in error patterns found after the detection of a differentially encoded signal, which show double symbol errors (i.e., two successive symbol errors); thus, error-correction capability for FEC methods (especially, for a random FEC method) may not be sufficiently used. Therefore, in order to fully bring the correcting capability into the randomization of the double symbol errors found after the detection of a differentially encoded signal, the interleaving (method) is generally used.
FIG. 8 is a block diagram for explaining a conventional FEC method used for differential coding and modulation.
In the figure, at the transmission side, a digital signal to be transmitted is input into terminal 52. The information bit rate of this digital signal is indicated by "fb". The signal input into terminal 52 is FEC-encoded by FEC encoder 53.
The output from the FEC encoder 53 is input into interleaver 54, where the bit-order of the output is converted. The output from interleaver 54 is input into differential encoder 55, where differential encoding is performed. The output from the differential encoder 55 is input into binary phase shift keying modulator 56 to be modulated. The output from the modulator 56 is transmitted via transmission path 57.
At the receiving side, the signal received from the transmission path 57 is demodulated and decoded by differential detector 58. The output form the differential detector 58 is input into deinterleaver 59 where inverse conversion with respect to the conversion performed in interleaver 54 is performed. In this way, double symbol errors appearing after the differential detection are randomized; therefore, successive errors are dispersed. The output from deinterleaver 59 is FEC-decoded in FEC decoder 60. The output from FEC decoder 60 is then output from terminal 61. The information bit rate of the signal output from terminal 61 is the same as "fb" of the signal which was input into terminal 52.
However, in this arrangement, it is necessary to provide an interleaver at the transmission side and a deinterleaver at the receiving side; thus, there has occurred a first problem in which the circuit size and the amount of transmission delay increase.
In addition, in the case of transmitting plural digital signals via plural parallel channels in the above-explained conventional system of using the FEC method together with the differential coding and modulation method, if error bit position detecting circuits are respectively provided for the FEC with respect to each channel, the circuit size of the system becomes larger. In particular, if the number of bits to be corrected becomes large, the amount of bit position information for FEC increases. Accordingly, there has occurred a second problem in which the size of the error bit position detecting circuits for correcting these error bits becomes larger.